Variables

Symbol	Quantity	Unit
t_pd	Propagation delay (average)	s
t_pHL	High-to-low propagation delay	s
t_pLH	Low-to-high propagation delay	s

What it means

Propagation delay t_pd is the average time it takes for a signal to pass through a logic gate from input to output. It is typically calculated as the average of the high‑to‑low (t_pHL) and low‑to‑high (t_pLH) delays. The delay affects the maximum operating frequency of a digital system. Fast gates have shorter propagation delays. Propagation delay is affected by load capacitance, supply voltage, and temperature. In timing analysis, it is used to determine the critical path and to ensure setup and hold times are met. Example: If a gate has t_pHL = 5ns and t_pLH = 7ns, then t_pd = (5+7)/2 = 6ns. This means the output appears about 6ns after the input changes, limiting the clock frequency to roughly 1/(2*t_pd) for a flip‑flop.

Worked example

Common mistakes

Watch unit consistency and the assumptions behind the formula; misapplying it outside its valid conditions is the most frequent error.

Applications

Propagation delay t_pd is the average of high‑to‑low and low‑to‑high delays of a logic gate. It defines the switching speed of digital circuits and limits the maximum clock frequency. Engineers use it to analyse timing constraints, to ensure correct operation in synchronous systems, and to optimise the performance of digital designs. By understanding propagation delays, they can avoid setup and hold time violations. This parameter is crucial for high‑speed digital design, including processors, FPGAs, and ASICs.

• Timing analysis and clock frequency optimisation
• Setup and hold time verification in sequential circuits
• Critical path analysis and speed improvement
• Selection of logic families for performance requirements
• Educational understanding of gate delay